1. Field of the Invention
This invention relates to a method for manufacturing a memory cell, more particularly to a low cost method for manufacturing a memory cell which has a high capacitance coupling ratio and a high integrity.
2. Description of the Related Art
Referring to FIG. 1, a first type of a conventional memory cell is shown. The conventional memory cell has a so-called flat cell structure and is manufactured in the following manner: field oxidizing a substrate so as to form a field oxide layer over the substrate; removing a portion of the field oxide layer so as to form two field oxide layers that are spaced by a channel; depositing a gate oxide layer over remaining portions of the field oxide layer and over the exposed substrate; removing a portion of the gate oxide layer which is over the channel; depositing a first polysilicon layer over remaining portions of the gate oxide layer and over the exposed substrate; growing an insulating layer over the first polysilicon layer; providing a first mask on the insulating layer, the first mask extending along the channel and having a length shorter than that of the insulating layer, the first mask further having two end portions which overlap respectively the remaining portions of the field oxide regions; etching the insulating layer and the first polysilicon layer that are not covered by the first mask; depositing a second polysilicon layer over a remaining portion of the insulating layer and over the exposed gate oxide layer; providing a second mask on the second polysilicon layer to define a control gate region, the second mask having a width narrower than that of the second polysilicon layer; etching portions of the second polysilicon layer that are not covered by the second mask so as to form a control gate; removing the second mask; providing a third mask on a remaining portion of the second polysilicon layer; etching the insulating layer and the first polysilicon layer so as to form a floating gate beneath the control gate; and removing the third mask.
Since the two end portions of the floating gate 12 of the conventional memory cell manufactured in the above-described conventional method overlap respectively the remaining portions of the field oxide layer due to the first mask, the conventional memory cell of FIG. 1 has a high capacitance coupling ratio which can be approximated by dividing the area of the floating gate 12 by the total area of the floating gate 12 and the channel and which is at least greater than 0.7. It should be noted that, a memory cell having a high capacitance ratio has a good writing characteristic. However, the occupied cell size of the memory cell shown in FIG. 1 is relative large, thus, high integrity cannot be achieved. Furthermore, a trench effect caused by excessive etching will occur around the drain terminal such that the drain terminal impedance is relative high, thereby slowing the operating speed of the memory cell.
Referring now to FIG. 2, a second type of a conventional memory cell is shown. The conventional memory cell also has a flat cell structure and is manufactured in the following manner: implanting impurities into a substrate so as to form first and second buried regions that are spaced by a channel; depositing a gate oxide layer over the substrate; removing a portion of the gate oxide layer which is over the channel; depositing a first polysilicon layer over remaining portions of the gate oxide layer and over the exposed substrate; growing an insulating layer over the first polysilicon layer; providing a first mask on the insulating layer, the first mask extending along the channel and having a length equal to that of the channel; etching the insulating layer and the first polysilicon layer that are not covered by the first mask; depositing an oxide layer over a remaining portion of the insulating layer and the exposed gate oxide layer; etching the oxide layer down to the insulating layer by the method of etchback so as to protect the buried regions; depositing a second polysilicon layer over the remaining portion of the insulating layer and over remaining portions of the oxide layer; providing a second mask on the second polysilicon layer to define a control gate region, the second mask having a width narrower than that of the second polysilicon layer; etching portions of the second polysilicon layer that are not covered by the second mask so as to form a control gate; removing the second mask; providing a third mask on a remaining portion of the second polysilicon layer; etching the insulating layer and the first polysilicon layer so as to form a floating gate beneath the control gate; and removing the third mask.
Since the two end portions of the floating gate 20 of the conventional memory cell shown in FIG. 2 do not overlap respectively the buried regions due to the first mask, the occupied cell size of the conventional memory cell of FIG. 2 is relatively small. Thus, a relatively high integrity can be achieved. However, since the length of the floating gate 20 is equal to that of the channel, the conventional memory cell shown in FIG. 2 has a low capacitance coupling ratio, which is approximately equal to 0.5. Moreover, while the purpose of the etchback step is to prevent the occurrence of the trench effect, etchback is difficult to control in mass production and complicates the manufacturing process.
Furthermore, the step of providing a third mask and the step of removing the third mask in the above-described conventional methods for manufacturing the conventional memory cells of FIGS. 1 and 2, are both cost-ineffective and time-consuming steps. Moreover, since an undercut will occur due to excessive etching when the insulating layer and the first polysilicon layer are etched, a so-called stringer will occur by squeezing the polysilicon of the second polysilicon layer into the undercut after the deposition of the second polysilicon layer so that the control gates of all of the memory cells which are connected in parallel are connected to one another, thereby resulting in cell failure.